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2019 News

   
 
 

Séminaire INHP@CT:

Driven Development philosophy and 9 years usage feedback for research in HPC

Monday july 8, 2019, Ter@tec Campus.

Sébastien VALAT, Engineer at ATOS/BULL.
 


Summary
"Nowadays HPC systems still continue growing and offer capabilities to handle more and more complex simulations. It goes with a large increase in complexity to be managed by the engineers and researchers who develop the software stack. Test Driven Development (TDD) is a well-known technic in many fields now, more on the Java, python and web world. On the HPC side, this is not so often used or known for many reasons: legacy codes/languages, research developments, not trained developers.... "

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Publication on the Joliot-Curie big challenges

June 2019


The diversity and interest in using compute-intensive computing to support numerical simulation modeling has once again been highlighted by the exceptional results presented in this issue, sometimes even the "world firsts", obtained by these pioneers of calculation.

Read in french


 

Séminaire INHP@CT:

Retour d'expérience : gestion de configuration et intégration continue.

Friday june 21, 2019 au Ter@tec Campus.

Olivier DELHOMME and Thomas MEJEAN, System Administrators at CEA DRF in Evry, presented their work «Feedback: configuration management and continuous integration.
 


Summary
"We will present how we manage server configuration and how we can instantiate applications for puppet users using concrete examples. Finally, we will see how we empower users through the integration and continuous deployment with gitlab and rundeck associated with the openstack infrastructure. "


 

14th TERATEC Forum, June 11 & 12, 2019

The TERATEC Forum is a major event in France and Europe that brings together the best international experts in HPC, Simulation and Big Data. It reaffirms the strategic importance of these technologies for developing industrial competitiveness and innovation capacity.

As part of its activities related to HPC, the CEA DAM Île-de-France is naturally represented as every year.

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June 3, 2019

Inauguration of Joliot-Curie, the French supercomputer

dedicated to French and European research

At 9.4 petaflops, Joliot-Curie is France’s third supercomputer and is set to become the most powerful French research supercomputer in 2020 when it reaches 22 petaflops. Designed by the European leader in supercomputing, Atos, for the French national high-performance computing organisation (GENCI), this new supercomputer located at the CEA’s Very Large Computing Centre (TGCC) was inaugurated on 3 June 2019 by François Jacq, CEA Chairman, Thierry Breton, Atos CEO, and Philippe Lavocat, GENCI CEO.

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May 2019

Summer Schools CEA-EDF-INRIA 2019

  • Numerical analysis, from may 13 to may 17, 2019
  • Computer science, from june 24 to june 28, 2019
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Ecole d'été 2019

 

Better understanding of the climate system through digital simulation
News release

March 26, 2019

French scientists offer strong contribution to coordinated international effort to better understand the climate system through computer simulations.

Climate scientists at the Institut Pierre Simon Laplace (IPSL) and CNRM-CERFACS announce today the release of new datasets that promise to provide fresh insights into past and future climate change. IPSL and CNRM-CERFACS are engaged, with other climate research centres, in an international effort to provide a new generation of climate change experiments.

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TGCCThe computing center of CEA located in Bruyères-le-Châtel which houses the Joliot-Curie supercomputers, as well as Cobalt of the CCRT.
©P. Stroppa/CEA


 

Séminaire INHP@CT: Programming for In-Memory Computing

Friday january 18, 2019, Ter@tec Campus.

Maha Kooli, researcher at the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier, will present his work on PProgramming In-Memory
 


Summary
In-Memory Computing (IMC) corresponds to a new data computation concept that brings the computing operations inside the memory units. It has been introduced to overcome the von Neumann bottleneck in terms of data transfer rate and power consumption.
A new IMC system based on SRAM architecture is introduced. It permits performing logic operations (and, or, xor, etc), arithmetic operations (addition, subtraction, etc), and memory operations (set, reset, write, etc). IMC system permits highly parallel computation inside the memory.
At the current research stage, the circuit-level design of the IMC system has not been completed yet. We therefore introduce a dedicated software platform based on LLVM that includes emulation tools to early experiment and evaluate how applications can take advantage of the IMC system. We evaluate the execution time and the energy consumption and we compare to conventional CPU-based systems. We target different application scenarios in various fields (image processing, cryptography, intensive computation).

Salle Valadon, Campus Ter@tec, 11h – 45 min.

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June 2019